In the area of data processors, a pipeline system is a system having computational and combinational capabilities divided into several sequential stages, each of which may be active with an independent set of data at the same instant of time. Data is viewed as flowing from one pipeline stage where it is acted upon or processed to another for further action or processing. To increase pipeline throughput new data is fed to the first stages thereof while old data is still being acted upon in the latter stages. Maximum throughput wherein all stages are busy all of the time is a goal seldom achieved in any pipeline system over an extended period of time.
Often the pipeline system is microprogrammable wherein each stage thereof responds to microinstructions. For example, an arithmetic element stage may respond to microinstructions requesting arithmetic operations such as add, divide, multiply, etc., and to other control instructions requesting Boolean operations to be performed. A simple memory stage may be requested by a control microinstruction to read from a particular address, and to output to a particular bus, register or stage, or to store data in a particular address.
In microprogrammable pipeline system design striving to maximize throughout, the task of providing the proper control microinstructions to the various stages in correct sequential order becomes quite complex, see "The Microprogramming of Pipelined Processors", P. M. Kogge, THE FOURTH ANNUAL SYMPOSIUM ON COMPUTER ARCHITECTURE, pp 63-69.
In a large pipelined system comprising a plurality of microprogrammable stages, microinstructions for controlling the stages may be stored as templates in an addressable template micromemory store to be provided automatically and sequentially to the stages of the pipeline system. See, for example, U.S. Pat. No. 4,101,960, issued July 18, 1978 in the name of R. A. Stokes et al disclosing and claiming therein a scientific processor utilizing a parallel pipeline array under template control.
However, for a complex pipeline system capable of performing a vast number of different operations, the number of templates and therefore the size of the template micromemory store becomes increasingly large and expensive to implement. Further, the template structure is quite inflexible when each stored template specifies the specific operation to be performed by a pipelined stage. In such a system, the introduction of new and different operations for execution by the pipelined stages, no matter how simple, requires an addition or change to the template micromemory structure and associated hardware.